Computer systems (e.g., integrated microcomputers) comprise processors (e.g., a central processing unit CPU, memory units (e.g., a random access memory RAM), busses, and other components. Interfaces exchange data and control information between these components and peripheral devices (e.g., displays, printers, buzzers). For example, the processor writes data to the memory and the interface sends this data to the peripheral device, or vice versa. To save processor resources, it is convenient to control the interfaces partly or completely independent from the processor. The interface transfers data from the memory or to the memory in so-called queues. A queue is usually a set of data entries in the memory which is identified by a start address and an end address. Usually, the processor tells the interface these addresses through registers. But communication via registers is inconvenient, because of the use of software and processor resources. Other disadvantages of prior art interfaces are explained later.
A queued serial peripheral interface unit (QSPI) is incorporated in many microcomputers and peripherals. The following references are useful: U.S. Pat. No. 4,958,277 [1] and 4,816,996 [2] both to Hill et al., and "Queued Serial Module (QSM) Reference Manual" by Motorola, Inc. 1991, order number QSMRM/AD [3].
The present invention seeks to provide a computer system with an improved interface and an improved method which mitigate or avoid these and other disadvantages and limitations of the prior art.